TPUS KraneShares Public-Private TPU and Next-Gen Computing ETF

The Fund seeks growth of capital by investing at least 80% of its net assets (plus borrowings for investment purposes) in the publicly-traded or privately offered securities of TPU and Next-Gen Computing companies and other instruments that have economic characteristics similar to such securities. In the case of publicly-traded securities, KraneShares determines whether a company is a “TPU and Next-Gen Computing” company based on its proprietary assessment of whether the company derives at least 50% of its revenue, gross profit or revenue growth contribution from designing, manufacturing, licensing or supplying the following:

• Custom AI Silicon Design: Computer processors, related intellectual property (“IP”) and/or processor architecture for artificial intelligence (“AI”) accelerator chips, including tensor processing units that accelerate the operation, training and inference of large-scale neural network models (“TPUs”), AI application-specific integrated circuits (“ASICs”), and next-generation neural processing units that are purpose-built for AI inference, transformer-based or large language model (“LLM”) workloads.
• Advanced Semiconductor Foundry & Packaging: Advanced-node logic fabrication of three nanometers or below, advanced semiconductor assembly techniques that physically integrate multiple distinct silicon dies that enable the high-bandwidth, low-latency die-to-die communication required for AI accelerator performance at scale and outsourced semiconductor assembly and test (“OSAT”) services for AI chiplet packages.
• High-Bandwidth Memory: High-bandwidth memory (“HBM”) stacked directly on or adjacent to AI accelerator dies, enabling wafers, specialty DRAM cell process technologies, and testing and characterization services for HBM production. For these purposes, HBM means stacked memory architecture in which multiple DRAM dies are vertically integrated using through-silicon vias (“TSVs”) and mounted in close physical proximity to the compute die, providing substantially higher memory bandwidth than conventional DRAM at lower power consumption per bit.
• Advanced PCB, Substrates & Materials: Chemicals, photomasks, or specialty gases used in advanced logic fabrication, advanced build-up substrates, insulating film substrates (“laminates”) in advanced flip-chip ball grid array (“FC-BGA”) integrated circuit packages (“Ajinomoto Build-up Film” or “ABF”), high-frequency or high-speed printed circuit board (“PCB”) materials (including laminates), and specialty dielectric materials and copper foil, which are required for AI server boards and high-density interconnect packages.
• Optical Interconnect & Photonics: Photonic or optical components that enable the ultra-high-bandwidth, energy-efficient data center interconnects and cluster-to-cluster communications infrastructures required to scale AI computer clusters to multi-gigawatt capacity, such as optical circuit switch (“OCS”) systems, MEMS-based optical mirror arrays and related photonic switching components, and integrated optical transceivers within or immediately adjacent to the compute switch or processor package (“co-packaged optics” or “CPO”) or optical compute interconnect (“OCI”).
• Precision Timing, Power Management & Signal Integrity: Precision timing components embedded within high-speed optical modules, network interface cards, AI accelerator boards or data center switching infrastructure, power management semiconductors, voltage regulators, and power delivery systems optimized for high-density AI server rack architectures, and signal integrity components that condition and amplify electrical and optical signals within high-speed interconnects inside AI accelerator systems.
• Next-Generation Computing Architectures: Computing architectures optimized for AI inference economics, including wafer-scale AI processors, photonic computing systems, in-memory or near-memory compute architectures, and purpose-built inference silicon designed to materially improve the performance-per-watt and cost-per-token economics of large-scale AI inference workloads at commercially viable scale, and hardware, software frameworks, or compiler toolchains that allow inference-optimized architectures to execute transformer-based or LLM workloads as an alternative to conventional GPU-based compute.

Subject to Completion: The information in this advertisement is not complete and may be changed. We may not sell securities until the registration statement filed with the Securities and Exchange Commission is effective. This advertisement is not an offer to sell these securities and is not soliciting an offer to buy these securities in any state where the offer or sale is not permitted.